Interactive Hardware-as-Code Course

Building the Eurorack Buffered Multiple in Python with SKiDL

Start from an empty Python file and progressively grow a complete, production-ready 3-channel Eurorack Buffered Multiple (buffered_multiple.py), 4HP PCB layout plan, mated 3U front panel generator, and automated pre-fabrication design audit—with every line of Python code, linter check, and verification output shown right on the page.

flowchart LR
  L1["0001: Empty File →<br/>Pre-Import Header & ERC"] --> L2["0002: Part Discovery →<br/>+ FP_* & LCSC_* Constants"]
  L2 --> L3["0003: Grow Script →<br/>+ eurorack_power()"]
  L3 --> L4["0004: Grow Script →<br/>+ buffered_channel_1to3()"]
  L4 --> L5["0005: Complete Circuit →<br/>1:3/1:6/1:9 & JLCPCB BOM"]
  L5 --> L6["0006: 4HP PCB Layout →<br/>tstamps & B.Cu/F.Cu Split"]
  L6 --> L7["0007: 4HP Front Panel →<br/>+6.48 mm Bushing Offset"]
  L7 --> L8["0008: Pre-Fab Audit →<br/>5/5 Automated Checks"]

How the course progresses from a 0-line script in Lesson 0001 to a complete 3-channel netlist, 4HP PCB & front panel generator, and automated pre-fab design audit in Lesson 0008.

Course Lessons (Start from Nothing & Grow to Production Hardware)

Lesson 0001 · Stage 1 ✓ ERC 0/0 · Ruff Clean

From Empty File to KiCad 10 Bootstrap & First `ERC()`

Start with a blank script, configure Python 3.14 with uv, write the pre-import KiCad 10 environment header, and run a 0-warning ERC() smoke check.

Code Grown: 0 → 72 lines (Pre-import os.environ, TEMPLATE, POWER, ERC())
Tooling Skill: uv venv --python 3.14, # noqa: E402, post-run ruff

./apps/0001-environment-and-kicad-bootstrap Start →

Lesson 0002 · Stage 2 ✓ ERC 0/0 · Ruff Clean

Programmatic Part Discovery & Adding `FP_` / `LCSC_` Constants

Write a Python discovery script to inspect KiCad 10 pinouts and footprints, query live JLCPCB stock, and grow our circuit script with verified FP_* and LCSC_* constants.

Code Grown: Full discover_parts.py + Stage 2 FP_* & LCSC_* constants
Tooling Skill: part.pins, u.p[n] vs u["V+"], part.fields["LCSC"]

./apps/0002-programmatic-component-discovery Start →

Lesson 0003 · Stage 3 ✓ ERC 0/0 · Ruff Clean

Growing the Script: Adding `eurorack_power(vcc, vee, gnd)`

Add the @subcircuit power block with the 10-pin IDC header, 1N5819WS Schottky reverse-polarity protection, and 10uF bulk caps.

Code Grown: Stage 2 → 155 lines (Full runnable power_subcircuit.py inline)
Tooling Skill: @subcircuit, multi-pin slice j_pwr[3..8], .net/.xml export

./apps/0003-eurorack-power-subcircuit Start →

Lesson 0004 · Stage 4 ✓ ERC 0/0 · Ruff Clean

Growing the Script: Adding `buffered_channel_1to3()`

Add the 1-to-3 op-amp channel subcircuit (TL074H, PESD12VL1BA TVS diode, U1A input buffer, and 3 loop-generated 470R output followers with builtins.NC).

Code Grown: 155 → 255 lines (Full runnable single_channel.py inline)
Tooling Skill: Series & operator, tuple-loop stage wiring, builtins.NC

./apps/0004-single-buffered-channel Start →

Lesson 0005 · Stage 5 ✓ ERC 0/0 · Ruff Clean

Completing `buffered_multiple.py`: Cascaded Normalling & JLCPCB BOM

Add generate_jlcpcb_bom(), assign KiCad Power and Signal NetClass rules, and cascade Channels 1–3 (1:3 → 1:6 → 1:9).

Code Grown: 255 → 334 lines (Complete buffered_multiple.py inline)
Tooling Skill: NetClass, SMT CSV grouping, interactive normalling simulator

./apps/0005-cascaded-normalling-and-bom-export Start →

Lesson 0006 · Stage 6 ✓ ERC 0/0 · Ruff Clean

From `.net` Netlist to 4HP KiCad 10 PCB Layout & Single-Sided SMT Assembly

Parse deterministic SKiDL tstamps in buffered_multiple.net, partition the 29 B.Cu SMD parts from the 15 F.Cu/B.Cu THT parts, and generate the 4HP (20 × 108 mm) 2×6 jack placement grid.

Code Grown: inspect_netlist_and_layout.py (357 lines inline + placement CSV)
Tooling Skill: S-expression .net parsing, hierarchical tag UUIDs, B.Cu vs. F.Cu split

./apps/0006-kicad-pcb-layout-and-assembly Start →

Lesson 0007 · Stage 7 ✓ ERC 0/0 · Ruff Clean

Automated 4HP Eurorack Front Panel Generation (`+6.48 mm` Bushing Offset)

Transform main-PCB WQP-PJ398SM (Thonkiconn) jack coordinates into Doepfer A-100 3U × 4HP (20 × 128.5 mm) panel drill holes and export a standalone .kicad_pcb front panel in Python.

Code Grown: generate_panel_plan.py (335 lines inline + .kicad_pcb exporter)
Tooling Skill: +6.48 mm bushing offset math, interactive coordinate calculator, UUIDv5

./apps/0007-eurorack-front-panel-generator Start →

Lesson 0008 · Stage 8 (Capstone) ✓ 5/5 Pre-Fab Audits · Ruff Clean

Programmatic Pre-Fab Design Review: Netlist-to-PCB Audit, DRC & Gerber Checks

Examine the 9 real-world layout bugs caught before fabrication and write a 5-stage Python audit script verifying TL074H phase-inversion immunity, thermal dissipation, rail headroom, pin connectivity, and SMT BOM partitioning.

Code Grown: prefab_design_audit.py (383 lines inline · 5/5 automated checks)
Tooling Skill: Programmatic netlist/BOM assertions, kicad-cli pcb drc, DFM/EMC triage

./apps/0008-prefab-design-review-and-drc Start →

Building the Eurorack Buffered Multiple in Python with SKiDL

Course Lessons (Start from Nothing & Grow to Production Hardware)

From Empty File to KiCad 10 Bootstrap & First `ERC()`

Programmatic Part Discovery & Adding `FP_` / `LCSC_` Constants

Growing the Script: Adding `eurorack_power(vcc, vee, gnd)`

Growing the Script: Adding `buffered_channel_1to3()`

Completing `buffered_multiple.py`: Cascaded Normalling & JLCPCB BOM

From `.net` Netlist to 4HP KiCad 10 PCB Layout & Single-Sided SMT Assembly

Automated 4HP Eurorack Front Panel Generation (`+6.48 mm` Bushing Offset)

Programmatic Pre-Fab Design Review: Netlist-to-PCB Audit, DRC & Gerber Checks

Reference Sheets (Printable)

SKiDL API & Pin Indexing Cheat Sheet

KiCad 10 Symbol, Footprint & JLCPCB Lookup Reference

Eurorack Power & Audio Jack Normalling Reference

SKiDL & Eurorack Hardware Glossary