SKiDL & Eurorack Hardware Glossary

Canonical definitions for SKiDL constructs, KiCad 10 library concepts, and JLCPCB manufacturing terms used across all lessons and learning records.

SKiDL & KiCad 10 Concepts

Template Part (dest=TEMPLATE)

A blueprint Part object configured with a symbol, footprint, and part.fields dictionary that is excluded from the active circuit until called to instantiate one or more concrete components.
Avoid: Prototype part, dummy part, abstract component.

Part Fields Dictionary (part.fields)

The dictionary on a SKiDL Part that persists custom key-value metadata (such as LCSC, MPN, and JLCPCB_Class) into exported KiCad netlists (.net), XML BOMs (.xml), and template clones.
Avoid: Part attributes, custom properties, object attributes.

Numeric Pin Accessor (part.p[n])

SKiDL's explicit pin-number lookup index that resolves a pin strictly by its physical package pin number n, avoiding collisions when multi-unit symbols (like TL074) repeat pin names such as "+" and "-".
Avoid: Pin array index, raw pin slice.

Power Drive Flag (net.drive = POWER)

A SKiDL net attribute declaring that an external power rail (+12V, -12V, GND) is actively energized, satisfying PWRIN pin checks during ERC().
Avoid: Power flag symbol, net voltage flag.

No-Connect Net (builtins.NC)

The special SKiDL net injected into Python's builtins module that marks an intentionally unused component pin (such as an output jack's TN switch contact) as unconnected during ERC().
Avoid: Floating pin, dummy net, skidl.NC.

Subcircuit Decorator (@subcircuit)

The SKiDL function decorator that registers a Python function as a hierarchical schematic module with its own local namespace and deterministic tag hierarchy.
Avoid: Child sheet macro, circuit class wrapper.

Net Routing Class (NetClass)

A SKiDL design rule object assigned to net.netclasses that embeds trace width, clearance, and priority constraints (such as Power vs. Signal) into exported KiCad netlists.
Avoid: Trace style, wire group.

Backup Symbol Library (<script>_sklib.py)

The Python file auto-generated by SKiDL at runtime caching the symbol definitions used by a circuit script so the script can re-run even if external KiCad .kicad_sym libraries move.
Avoid: Netlist cache, symbol dump.

JLCPCB & Eurorack Manufacturing

JLCPCB Basic Part

A high-demand SMT component pre-loaded on JLCPCB's pick-and-place machines that incurs zero feeder setup fee ($0) during PCBA manufacturing.
Avoid: Standard part, stock part.

JLCPCB Extended Part

An SMT component in the JLCPCB/LCSC catalog that requires manual reel loading onto a pick-and-place feeder for each order (typically incurring a per-unique-MPN feeder fee).
Avoid: Special part, custom part.

Switched Tip Normal Contact (TN)

The internal leaf-spring contact on a switched 3.5mm jack (WQP-PJ398SM / AudioJack2_SwitchT) that conducts to the Tip (T) when unpatched and mechanically disconnects when a plug is inserted.
Avoid: Normal pin, shunt pin, break contact.

Deterministic Tag Timestamp (tag / tstamps)

The stable UUID exported in a KiCad .net file by hashing a SKiDL @subcircuit and Part tag= path (such as /ch1/u_ch1), allowing KiCad's pcbnew netlist importer to update footprints in-place across Python regenerations.
Avoid: Random component ID, transient netlist handle.

Bushing Offset (+6.48 mm)

The mechanical displacement in KiCad's WQP-PJ398SM (Thonkiconn) footprint between its (0, 0) origin at Pad S (Sleeve) and the threaded M6 bushing shaft center at (0, +6.48 mm) (for vertical 0° placement).
Avoid: Footprint center, pad origin.

Design Rules Check (DRC)

KiCad's physical PCB layout verification (kicad-cli pcb drc --refill-zones) that checks copper-to-copper clearances, copper-to-edge margins, trace widths, and unrouted or isolated net islands after netlist import.
Avoid: Schematic ERC, syntax lint.